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The Formal Methods in Systems Engineering Group at Vienna University of Technology
(headed by Prof. Helmut Veith)
is concerned with research and development in the following
fields: |
| Formal Methods for Embedded Systems | |
| We develop formal methods to analyze and design embedded systems. Application areas include industrial automotive and avionic software. Our research focuses on model checking, timing analysis, and testing. | |
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Modelling Embedded Software
Model based development of embedded systems |
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Testing and Validation of Runtime Resources
Modeling and validating runtime resources of safety-critical embedded systems. |
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Fortas - Execution Time Analysis
Execution time analysis for embedded software. |
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Runtime Reflection
In this project we focus on techniques which allow software systems to analyse their own behavior with respect to certain correctness properties. |
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| Model Checking and Constraint Solving | |
| We bring together the theory and technology which powers model checkers and software analysis tools. | |
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Software Security
Verification of security properties and malicious code detection in x86 executables. |
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Constraint Solvers
Solving mixed Boolean and arithmetic systems |
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| Automata, Logic, and Complexity | |
| Mathematical methods and models for problems in computer science. | |
